Specifications
2.5.5.3 Synchronous Timings (SRAM)
Table 2-15. External Bus Synchronous Timings (SRAM Access)3
80 MHz
100 MHz
No.
Characteristics
Expression1,2
Unit
Min
Max
Min
Max
196
197
198
199
200
201
202
203
CLKOUT high to BS assertion
0.25 × T +5.2/–0.5
2.6
8.4
—
8.3
13.6
5.6
—
2.0
6.5
—
7.7
11.7
5.0
—
ns
ns
ns
ns
ns
ns
ns
C
CLKOUT high to BS deassertion
CLKOUT high to address, and AA valid
0.75 × T +4.2/–1.0
C
4
0.25 × T + 2.5
C
4
CLKOUT high to address, and AA invalid
TA valid to CLKOUT high (setup time)
CLKOUT high to TA invalid (hold time)
CLKOUT high to data out active
0.25 × T – 0.7
2.4
5.8
0.0
3.1
1.8
4.0
0.0
2.5
C
—
—
—
—
0.25 × T
—
—
C
CLKOUT high to data out valid
80 MHz:
0.25 × T + 4.5
—
7.6
—
—
ns
C
100 MHz:
0.25 × T + 4.0
—
—
—
—
6.5
—
ns
ns
C
204
205
CLKOUT high to data out invalid
0.25 × T
3.1
2.5
C
CLKOUT high to data out high impedance
80 MHz:
0.25 × T + 0.5
—
3.6
—
—
ns
C
100 MHz:
0.25 × T
—
5.0
—
—
—
—
2.5
—
ns
ns
ns
C
206
207
208
Data in valid to CLKOUT high (setup)
CLKOUT high to data in invalid (hold)
CLKOUT high to RD assertion
4.0
0.0
6.7
0.0
—
maximum:
10.4
ns
ns
0.75 × T + 2.5
11.9
4.5
10.0
4.0
C
209
210
CLKOUT high to RD deassertion
0.0
7.6
0.0
4.5
ns
ns
2
CLKOUT high to WR assertion
0.5 × T + 4.3
10.6
9.3
C
[WS = 1 or WS ≥ 4]
[2 ≤ WS ≤ 3]
1.3
0.0
4.8
4.3
0.0
0.0
4.3
3.8
ns
ns
211
CLKOUT high to WR deassertion
Notes: 1. WS is the number of wait states specified in the BCR.
2. If WS > 1, WR assertion refers to the next rising edge of CLKOUT.
3. External bus synchronous timings should be used only for reference to the clock and not for relative timings.
4. T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set. Use the status of BR
(See T212) to determine whether the access referenced by A[0–23] is internal or external in this mode.
DSP56301 Technical Data, Rev. 10
2-28
Freescale Semiconductor
FREESCALE [ Freescale ]
