AC Electrical Characteristics
Table 2-18. Universal Bus Mode Timing Parameters (Continued)
80 MHz
100 MHz
No.
Characteristic
Expression
Unit
Min Max
Min Max
3
345 HDBDR High from Read Data Strobe Deassertion
—
—
22.2
22.2
—
—
19.6
19.6
ns
ns
2
346 HRST Assertion to Host Port Pins High Impedance
Notes: 1. The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
2. HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.
3. The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
4. The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
5. HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if
programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.
6. HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.
7. “LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.
LT ≥ 1.
8. Values are valid for V = 3.3 0.3V
CC
Table 2-19. Universal Bus Mode, Synchronous Port A Type Host Timing
80 MHz
100 MHz
No.
Characteristic
Expression
Unit
Min Max
Min Max
300 Access Cycle Time
3 × T
37.5
5.8
0.0
4.1
2.5
—
—
—
—
—
—
7.6
30.0
4.6
0.0
3.3
2.0
—
—
—
—
—
ns
ns
ns
ns
ns
C
1
301 HA[10–0], HAEN Setup to Data Strobe Assertion
1
302 HA[10–0], HAEN Valid Hold from Data Strobe Deassertion
1
305 Data Strobe Deasserted Width
307 HBS Asserted Pulse Width
1
308 HBS Assertion to Data Strobe Assertion
80 MHz: T − 4.9
ns
ns
C
100 MHz: T − 4.0
—
6.0
—
C
1
309 HBS Assertion to Data Strobe Deassertion
80 MHz: 2.5 × T + 2.9
100 MHz: 2.5 × T + 2.3
34.1
22.1
—
—
ns
ns
C
27.3
C
1
310 HBS Deassertion to Data Strobe Deassertion
80 MHz: 1.5 × T + 3.3
100 MHz: 1.5 × T + 2.6
ns
ns
C
17.6
1.3
—
—
—
C
3
312 Data Out Active from Read Data Strobe Assertion
1.7
—
—
ns
ns
313 Data Out Valid from Read Data Strobe Assertion
18.9
16.9
3
(No Wait States Inserted—HTA Asserted)
314 Data Out Valid Hold from Read Data Strobe Deassertion
1.7
—
—
12.0
—
1.3
—
—
9.6
—
ns
ns
ns
ns
ns
ns
ns
ns
3
3
315 Data Out High Impedance from Read Data Strobe Deassertion
4
316 Data In Valid Setup to Write Data Strobe Deassertion
8.3
0.0
0.0
—
6.6
0.0
0.0
—
4
317 Data In Valid Hold from Write Data Strobe Deassertion
—
—
1,2
324 HTA Assertion to Data Strobe Deassertion
—
—
1,2
325 HTA High Impedance from Data Strobe Deassertion
15.3
—
12.2
—
7
326 HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
327 Data Strobe Deasserted Hold from HIRQ Deassertion
(LT + 1) × T − 6.0
6.5
0.0
4.0
0.0
C
—
—
1
(HIRH = 0)
1
328 HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)
1.5 × T
18.8
—
—
15.0
—
—
ns
C
329 HIRQ Deassertion from Data Strobe Assertion
80 MHz: 2.5 × T + 24.7
100 MHz: 2.5 × T + 21.5
55.9
ns
ns
C
1
(HIRH = 1, HIRD = 1)
46.5
C
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-35
FREESCALE [ Freescale ]
