Specifications
Table 2-19. Universal Bus Mode, Synchronous Port A Type Host Timing (Continued)
80 MHz
100 MHz
Min Max
No.
Characteristic
Expression
Unit
Min Max
330 HIRQ High Impedance from Data Strobe Assertion
80 MHz: 2.5 × T + 24.7
—
55.9
ns
ns
C
1,6
(HIRH = 1, HIRD = 0)
100 MHz: 2.5 × T + 21.5
—
46.5
—
C
331 HIRQ Active from Data Strobe Deassertion
2.5 × T
31.3
—
25.0
ns
C
1
(HIRH = 1, HIRD = 0)
1
332 HIRQ Deasserted Hold from Data Strobe Deassertion
2.5 × T
31.3
—
—
22.2
—
25.0
—
—
19.6
—
ns
ns
ns
ns
C
2
346 HRST Assertion to Host Port Pins High Impedance
347 HBS Assertion to CLKOUT Rising Edge
4.3
7.4
3.4
5.9
1
348 Data Strobe Deassertion to CLKOUT Rising Edge
—
—
Notes: 1. The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
2. HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.
3. The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
4. The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
5. HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if
programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.
6. HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.
7. “LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.
8. Values are valid for V = 3.3 0.3V
CC
HA[10–0]
301
302
HDS
HRD
HWR
305
307
308
HBS
310
309
332
329
HIRQ
(HIRD = 1,
HIRH = 1)
328
331
330
HIRQ
(HIRD = 0,
HIRH = 1)
Figure 2-27. Universal Bus Mode I/O Access Timing
DSP56301 Technical Data, Rev. 10
2-36
Freescale Semiconductor
FREESCALE [ Freescale ]
