AC Electrical Characteristics
DRAM Type
(tRAC ns)
Note: This figure should be used for primary selection. For
exact and detailed timings, see the following tables.
100
80
70
60
Chip Frequency
(MHz)
50
120
40 66
80
100
4 Wait States
8 Wait States
11 Wait States
15 Wait States
Figure 2-17. DRAM Out-of-Page Wait States Selection Guide
Table 2-12. DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2
80 MHz
Characteristics3
No.
Symbol
Expression
Unit
Min
Max
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid (read)
161 CAS deassertion to data not valid (read hold time)
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
t
9 × T
112.5
—
—
52.9
21.6
31.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
C
t
4.75 × T − 6.5
RAC
C
t
2.25 × T − 6.5
—
CAC
C
t
3 × T − 6.5
—
AA
C
t
0.0
OFF
t
3.25 × T − 4.0
36.6
67.9
36.6
55.4
24.1
29.3
19.9
49.1
28.4
36.6
—
RP
C
t
t
5.75 × T − 4.0
—
RAS
C
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
3.25 × T − 4.0
—
RSH
CSH
C
t
4.75 × T − 4.0
—
C
t
t
2.25 × T − 4.0
—
CAS
C
167 RAS assertion to CAS assertion
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
170 CAS deassertion pulse width
2.5 × T
2
33.3
23.9
—
RCD
C
t
1.75 × T
2
RAD
CRP
C
t
4.25 × T − 4.0
C
t
2.75 × T − 6.0
—
CP
C
171 Row address valid to RAS assertion
t
3.25 × T − 4.0
—
ASR
C
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-21
FREESCALE [ Freescale ]
