Specifications
Table 2-10. DRAM Page Mode Timings, Three Wait States1, 2, 3
80 MHz
100 MHz
No.
Characteristics
Symbol
Expression
Unit
Min Max
Min Max
131 Page mode cycle time for two consecutive accesses of the
same direction
4 × T
50.0
—
40.0
—
ns
C
Page mode cycle time for mixed (read and write) accesses
132 CAS assertion to data valid (read)
t
3.5 × T
43.7
—
—
19.3
31.8
—
35.0
—
—
14.3
24.3
—
ns
ns
ns
ns
ns
ns
ns
PC
C
t
2 × T − 5.7
CAC
C
133 Column address valid to data valid (read)
134 CAS deassertion to data not valid (read hold time)
135 Last CAS assertion to RAS deassertion
136 Previous CAS deassertion to RAS deassertion
137 CAS assertion pulse width
t
3 × T − 5.7
—
—
AA
C
t
t
0.0
0.0
OFF
2.5 × T − 4.0
27.3
52.3
21.0
—
21.0
41.0
16.0
—
RSH
C
t
4.5 × T − 4.0
—
—
RHCP
C
t
2 × T − 4.0
—
—
CAS
C
5
138 Last CAS deassertion to RAS assertion
t
CRP
•
•
•
•
BRW[1–0] = 00
BRW[1–0] = 01
BRW[1–0] = 10
BRW[1–0] = 11
Not supported
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
3.75 × T − 6.0
40.9
53.4
78.4
31.5
41.5
61.5
C
4.75 × T − 6.0
C
6.75 × T − 6.0
C
139 CAS deassertion pulse width
t
1.5 × T − 4.0
14.8
8.5
—
—
11.0
6.0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CP
C
140 Column address valid to CAS assertion
141 CAS assertion to column address not valid
142 Last column address valid to RAS deassertion
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse width
t
t
T − 4.0
C
ASC
2.5 × T − 4.0
27.3
46.0
11.6
5.4
—
21.0
36.0
8.5
—
CAH
C
t
4 × T − 4.0
—
—
RAL
RCS
C
t
t
1.25 × T − 4.0
—
—
C
0.75 × TC − 4.0
—
3.5
—
RCH
WCH
t
2.25 × T − 4.2
23.9
39.3
42.6
36.3
2.0
—
18.3
30.5
33.2
28.2
0.2
—
C
t
3.5 × T − 4.5
—
—
WP
C
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
t
3.75 × T − 4.3
—
—
RWL
CWL
C
t
3.25 × T − 4.3
—
—
C
t
0.5 × T – 4.8
—
—
DS
C
t
2.5 × T − 4.0
27.3
11.3
39.8
—
—
21.0
8.2
—
DH
C
t
1.25 × T − 4.3
—
—
WCS
C
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
t
3.5 × T − 4.0
—
31.0
—
—
ROH
C
t
2.5 × T − 5.7
25.6
—
19.3
—
GA
C
6
154 RD deassertion to data not valid
t
0.0
0.0
GZ
155 WR assertion to data active
0.75 × T – 1.5
7.9
—
6.0
—
C
156 WR deassertion to data high impedance
0.25 × T
—
3.1
—
2.5
C
Notes: 1. The number of wait states for Page mode access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. The asynchronous delays specified in the expressions are valid for DSP56301.
4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t equals 4 ×
PC
T
for read-after-read or write-after-write sequences).
C
5. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-
access.
6. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
and not t
.
GZ
OFF
DSP56301 Technical Data, Rev. 10
2-18
Freescale Semiconductor
FREESCALE [ Freescale ]
