欢迎访问ic37.com |
会员登录 免费注册
发布采购

DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ Freescale ]
 浏览型号DSP56301VF100的Datasheet PDF文件第47页浏览型号DSP56301VF100的Datasheet PDF文件第48页浏览型号DSP56301VF100的Datasheet PDF文件第49页浏览型号DSP56301VF100的Datasheet PDF文件第50页浏览型号DSP56301VF100的Datasheet PDF文件第52页浏览型号DSP56301VF100的Datasheet PDF文件第53页浏览型号DSP56301VF100的Datasheet PDF文件第54页浏览型号DSP56301VF100的Datasheet PDF文件第55页  
AC Electrical Characteristics  
Table 2-14. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued)  
80 MHz  
100 MHz  
No.  
Characteristics3  
Symbol  
Expression  
Unit  
Min Max  
Min Max  
170 CAS deassertion pulse width  
t
6.25 × T – 6.0  
74.1  
74.1  
30.4  
5.4  
56.5  
58.5  
23.5  
3.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CP  
C
171 Row address valid to RAS assertion  
172 RAS assertion to row address not valid  
173 Column address valid to CAS assertion  
174 CAS assertion to column address not valid  
175 RAS assertion to column address not valid  
176 Column address valid to RAS deassertion  
177 WR deassertion to CAS assertion  
t
6.25 × T 4.0  
ASR  
C
t
2.75 × T 4.0  
RAH  
C
t
0.75 × T 4.0  
ASC  
C
t
6.25 × T 4.0  
74.1  
117.9  
83.5  
58.7  
18.2  
58.5  
93.5  
66.0  
46.2  
13.8  
CAH  
C
t
9.75 × T 4.0  
AR  
C
t
7 × T 4.0  
RAL  
C
t
5 × T 3.8  
RCS  
C
4
178 CAS deassertion to WR assertion  
t
1.75 × T – 3.7  
RCH  
C
4
179 RAS deassertion to WR assertion  
t
80 MHz:  
RRH  
0.25 × T 2.6  
0.5  
ns  
C
100 MHz:  
0.25 × T 2.0  
0.5  
55.8  
90.8  
150.5  
153.2  
138.2  
83.5  
58.5  
93.5  
90.7  
11.0  
43.5  
151.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
C
180 CAS assertion to WR deassertion  
181 RAS assertion to WR deassertion  
182 WR assertion pulse width  
t
t
6 × T 4.2  
70.8  
WCH  
WCR  
C
9.5 × T 4.2  
114.6  
189.3  
192.6  
173.8  
105.4  
74.1  
C
t
15.5 × T 4.5  
WP  
C
183 WR assertion to RAS deassertion  
184 WR assertion to CAS deassertion  
185 Data valid to CAS assertion (write)  
186 CAS assertion to data not valid (write)  
187 RAS assertion to data not valid (write)  
188 WR assertion to CAS assertion  
189 CAS assertion to RAS assertion (refresh)  
190 RAS deassertion to CAS assertion (refresh)  
191 RD assertion to RAS deassertion  
192 RD assertion to data valid  
t
15.75 × T 4.3  
RWL  
CWL  
C
t
14.25 × T 4.3  
C
t
8.75 × T 4.0  
DS  
C
t
6.25 × T 4.0  
DH  
C
t
t
9.75 × T 4.0  
117.9  
114.5  
14.8  
DHR  
C
9.5 × T 4.3  
WCS  
C
t
1.5 × T 4.0  
CSR  
C
t
t
4.75 × T 4.0  
55.4  
RPC  
C
15.5 × T 4.0  
189.8  
ROH  
C
t
80 MHz:  
GA  
14 × T 6.5  
168.5  
ns  
C
100 MHz:  
14 × T 5.7  
0.0  
9.1  
0.0  
6.0  
134.3  
ns  
ns  
ns  
ns  
C
3
193 RD deassertion to data not valid  
t
GZ  
194 WR assertion to data active  
0.75 × T – 1.5  
C
195 WR deassertion to data high impedance  
0.25 × T  
3.1  
2.5  
C
Notes: 1. The number of wait states for an out-of-page access is specified in the DCR.  
2. The refresh period is specified in the DCR.  
3. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t  
and not t  
.
GZ  
OFF  
4. Either t  
or t  
must be satisfied for read cycles.  
RCH  
RRH  
DSP56301 Technical Data, Rev. 10  
Freescale Semiconductor  
2-25  
 复制成功!