Specifications
Table 2-13. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued)
80 MHz
100 MHz
No.
Characteristics3
Symbol
Expression
Unit
Min Max
Min Max
187 RAS assertion to data not valid (write)
188 WR assertion to CAS assertion
t
7.75 × T − 4.0
92.9
77.0
14.8
30.4
139.8
—
—
—
—
—
73.5
60.7
11.0
23.5
111.0
—
—
—
—
—
ns
ns
ns
ns
ns
DHR
C
t
6.5 × T − 4.3
WCS
C
189 CAS assertion to RAS assertion (refresh)
190 RAS deassertion to CAS assertion (refresh)
191 RD assertion to RAS deassertion
192 RD assertion to data valid
t
1.5 × T − 4.0
CSR
C
t
2.75 × T − 4.0
RPC
C
t
11.5 × T − 4.0
ROH
C
t
80 MHz:
GA
10 × T − 6.5
—
118.5
—
—
ns
C
100 MHz:
10 × T − 7.0
—
0.0
9.1
—
—
—
—
0.0
6.0
—
93.0
—
ns
ns
ns
ns
C
3
193 RD deassertion to data not valid
t
GZ
194 WR assertion to data active
0.75 × T – 1.5
—
—
C
195 WR deassertion to data high impedance
0.25 × T
3.1
2.5
C
Notes: 1. The number of wait states for an out-of-page access is specified in the DCR.
2. The refresh period is specified in the DCR.
3. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
and not t
.
GZ
OFF
4. Either t
or t
must be satisfied for read cycles.
RCH
RRH
Table 2-14. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
80 MHz
100 MHz
Min Max
No.
Characteristics3
Symbol
Expression
Unit
Min Max
157 Random read or write cycle time
158 RAS assertion to data valid (read)
t
16 × T
200.0
—
160.0
—
ns
RC
C
t
80 MHz:
RAC
8.25 × T − 6.5
100 MHz:
—
—
96.6
—
—
—
—
ns
ns
C
8.25 × T − 5.7
76.8
C
159 CAS assertion to data valid (read)
t
80 MHz:
CAC
4.75 × T − 6.5
100 MHz:
—
—
52.9
—
—
—
—
ns
ns
C
4.75 × T − 5.7
41.8
C
160 Column address valid to data valid (read)
t
80 MHz:
AA
5.5 × T − 6.5
—
62.3
—
—
ns
C
100 MHz:
5.5 × T − 5.7
—
—
—
—
49.3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
161 CAS deassertion to data not valid (read hold time)
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
t
0.0
0.0
0.0
OFF
t
6.25 × T − 4.0
74.1
117.9
74.1
99.1
55.4
41.8
32.4
92.9
—
58.5
93.5
58.5
78.5
43.5
33.0
25.5
73.5
—
RP
C
t
t
9.75 × T − 4.0
—
—
RAS
C
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
6.25 × T − 4.0
—
—
RSH
CSH
C
t
8.25 × T − 4.0
—
—
C
t
4.75 × T − 4.0
—
—
CAS
C
167 RAS assertion to CAS assertion
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
t
3.5 × T
2
45.8
36.4
—
37.0
29.5
—
RCD
C
t
2.75 × T
2.0
RAD
CRP
C
t
7.75 × T − 4.0
C
DSP56301 Technical Data, Rev. 10
2-24
Freescale Semiconductor
FREESCALE [ Freescale ]
