AC Electrical Characteristics
Table 2-13. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2
80 MHz
100 MHz
No.
Characteristics3
Symbol
Expression
Unit
Min Max
Min Max
157 Random read or write cycle time
158 RAS assertion to data valid (read)
t
12 × T
150.0
—
120.0
—
ns
RC
C
t
80 MHz:
RAC
6.25 × T − 6.5
100 MHz:
—
—
71.6
—
—
—
—
ns
ns
C
6.25 × T − 7.0
55.5
C
159 CAS assertion to data valid (read)
t
80 MHz:
CAC
3.75 × T − 6.5
100 MHz:
—
—
40.4
—
—
—
—
ns
ns
C
3.75 × T − 7.0
30.5
C
160 Column address valid to data valid (read)
t
80 MHz:
AA
4.5 × T − 6.5
—
49.8
—
—
ns
C
100 MHz:
4.5 × T − 7.0
—
—
—
—
38.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
161 CAS deassertion to data not valid (read hold time)
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
t
0.0
0.0
OFF
t
4.25 × T − 4.0
49.1
92.9
61.6
74.1
42.9
27.3
17.9
67.9
49.1
49.1
17.9
5.4
—
38.5
73.5
48.5
58.5
33.5
21.0
13.5
53.5
36.5
38.5
13.5
3.5
—
RP
C
t
t
7.75 × T − 4.0
—
—
RAS
C
164 CAS assertion to RAS deassertion
165 RAS assertion to CAS deassertion
166 CAS assertion pulse width
5.25 × T − 4.0
—
—
RSH
CSH
C
t
6.25 × T − 4.0
—
—
C
t
t
3.75 × T − 4.0
—
—
CAS
C
167 RAS assertion to CAS assertion
2.5 × T
4.0
4.0
35.3
25.9
—
29.0
21.5
—
RCD
C
168 RAS assertion to column address valid
169 CAS deassertion to RAS assertion
170 CAS deassertion pulse width
t
1.75 × T
C
RAD
CRP
t
5.75 × T − 4.0
C
t
4.25 × T – 6.0
—
—
CP
C
171 Row address valid to RAS assertion
172 RAS assertion to row address not valid
173 Column address valid to CAS assertion
174 CAS assertion to column address not valid
175 RAS assertion to column address not valid
176 Column address valid to RAS deassertion
177 WR deassertion to CAS assertion
t
t
4.25 × T − 4.0
—
—
ASR
C
1.75 × T − 4.0
—
—
RAH
C
t
0.75 × T − 4.0
—
—
ASC
CAH
C
t
5.25 × T − 4.0
61.6
92.9
71.0
33.5
17.9
—
48.5
73.5
56.0
26.0
13.8
—
C
t
7.75 × T − 4.0
—
—
AR
C
t
t
6 × T − 4.0
—
—
RAL
C
3.0 × T − 4.0
—
—
RCS
RCH
RRH
C
4
178 CAS deassertion to WR assertion
t
t
1.75 × T – 3.7
—
—
C
4
179 RAS deassertion to WR assertion
80 MHz:
0.25 × T − 2.6
0.5
—
—
—
ns
C
100 MHz:
0.25 × T − 2.0
—
—
—
—
—
—
—
—
—
0.5
45.8
70.8
110.5
113.2
98.2
53.5
48.5
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
C
180 CAS assertion to WR deassertion
181 RAS assertion to WR deassertion
182 WR assertion pulse width
t
t
5 × T − 4.2
58.3
89.6
139.3
142.7
123.8
67.9
61.6
WCH
WCR
C
7.5 × T − 4.2
C
t
11.5 × T − 4.5
WP
C
183 WR assertion to RAS deassertion
184 WR assertion to CAS deassertion
185 Data valid to CAS assertion (write)
186 CAS assertion to data not valid (write)
t
11.75 × T − 4.3
RWL
CWL
C
t
10.25 × T − 4.3
C
t
5.75 × T − 4.0
DS
C
t
5.25 × T − 4.0
DH
C
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-23
FREESCALE [ Freescale ]
