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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
11.7 AC TIMING SPECIFICATIONS (See notes (a), (b), (c), and (d) corresponding to part operation,  
GND = 0 Vdc, TA = 0 to 70°C; see numbered notes; see Figures 11-211-11)  
3.3 V or  
5.0 V  
3.3 V  
5.0 V  
8.39 MHz  
16.78 MHz  
25.16 MHz  
Num.  
Characteristic  
Symbol  
Min  
0
Max  
Min  
0
Max  
30  
Min  
0
Max  
20  
Unit  
ns  
6
7
CLKOUT High to Address, FC, SIZ, RMC Valid  
t
60  
CHAV  
CLKOUT High to Address, Data, FC, SIZ, RMC  
High Impedance  
t
0
120  
0
60  
0
40  
ns  
CHAZx  
8
CLKOUT High to Address, FC, SIZ, RMC  
Invalid  
t
0
3
0
3
0
3
ns  
ns  
CHAZn  
9
9
CLKOUT Low to AS, DS, CS, IFETCH, IPIPE,  
IACKAsserted  
t
t
60  
30  
20  
CLSA  
STSA  
2
9A  
AS to DS or CS Asserted (Read)  
–30  
30  
30  
–15  
15  
15  
–6  
10  
6
ns  
ns  
11  
12  
13  
14  
Address, FC, SIZ, RMC Valid to AS, CS (and  
DS Read) Asserted  
t
AVSA  
CLKOUT Low to AS, DS, CS, IFETCH,  
IPIPE, IACKNegated  
t
3
60  
3
30  
3
20  
ns  
ns  
CLSN  
AS, DS, CS, IACKNegated to Address, FC,  
SIZ Invalid (Address Hold)  
t
30  
15  
10  
SNAI  
SWA  
AS, CS (and DS Read) Width Asserted  
t
200  
90  
100  
45  
70  
30  
30  
ns  
ns  
ns  
14A DS Width Asserted (Write)  
t
t
SWAW  
SWDW  
14B AS, CS, IACK(and DS Read) Width Asserted  
80  
40  
(Fast Termination Cycle)  
3
15  
AS, DS, CS Width Negated  
t
80  
30  
0
120  
40  
15  
0
60  
30  
30  
30  
30  
10  
0
40  
20  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SN  
16  
CLKOUT High to AS, DS, R/W High Impedance  
AS, DS, CS Negated to R/W High  
CLKOUT High to R/W High  
t
CHSZ  
SNRN  
CHRH  
CHRL  
RAAA  
RASA  
17  
18  
20  
t
t
t
t
t
60  
60  
CLKOUT High to R/W Low  
0
0
0
9
21  
R/ W High to AS, CS Asserted  
R/W Low to DS Asserted (Write)  
CLKOUT High to Data-Out Valid  
30  
140  
30  
15  
70  
15  
10  
47  
10  
22  
23  
24  
t
60  
CHDO  
Data-Out Valid to Negating Edge of AS, CS,  
(Fast Termination Write)  
t
DVASN  
25  
DS, CS, Negated to Data-Out Invalid (Data-Out  
Hold)  
t
30  
15  
10  
ns  
SNDOI  
26  
27  
Data-Out Valid to DS Asserted (Write)  
t
30  
10  
40  
15  
5
10  
5
ns  
ns  
ns  
DVSA  
Data-In Valid to CLKOUT Low (Data Setup)  
t
DICL  
27A Late BERR, HALT, BKPT Asserted to CLKOUT  
Low (Setup Time)  
t
20  
10  
BELCL  
28  
AS, DS Negated to DSACK, BERR, HALT  
Negated  
t
0
0
160  
0
0
80  
60  
0
0
50  
40  
ns  
ns  
ns  
SNDN  
4
29  
DS, CS Negated to Data-In Invalid (Data-In  
Hold)  
t
SNDI  
SHDI  
4
29A  
DS, CS Negated to Data-In High Impedance  
t
120  
11-8  
MC68340 USER’S MANUAL  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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