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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
11.7 AC TIMING SPECIFICATIONS (Continued)  
3.3 V or  
5.0 V  
3.3 V  
8.39 MHz  
5.0 V  
16.78 MHz 25.16 MHz  
Symbol Min Max Min Max Min Max  
Num.  
Characteristic  
Unit  
4
30  
CLKOUT Low to Data-In Invalid (Fast  
Termination Hold)  
t
30  
15  
10  
ns  
CLDI  
4
30A  
CLKOUT Low to Data-In High Impendance  
t
t
1
180  
100  
60  
1
90  
50  
30  
200  
30  
30  
1
60  
32  
20  
140  
20  
20  
ns  
CLDH  
5
31  
DSACKAsserted to Data-In Valid  
t
ns  
DADI  
31A DSACKAsserted to DSACKValid (Skew)  
ns  
ns  
DADV  
32  
33  
34  
HALT and RESET Input Transition Time  
CLKOUT Low to BG Asserted  
t
400  
60  
HRrf  
t
ns  
CLBA  
CLBN  
CLKOUT Low to BG Negated  
t
60  
ns  
6
35  
BR Asserted to BG Asserted (RMC Not  
Asserted)  
t
CLKOUT  
BRAGA  
37  
39  
BGACK Asserted to BG Negated  
BG Width Negated  
t
1
2
2.5  
1
2
2.5  
1
2
2.5 CLKOUT  
GAGN  
t
t
CLKOUT  
CLKOUT  
ns  
GH  
GA  
39A BG Width Asserted  
1
1
1
46  
R/W Width Asserted (Write or Read)  
t
300  
180  
150  
90  
100  
60  
RWA  
46A R/ W Width Asserted (Fast Termination Write or  
Read)  
t
ns  
RWAS  
8
47A  
Asynchronous Input Setup Time  
t
t
15  
30  
60  
60  
8, 5  
15  
30  
30  
5
10  
20  
20  
ns  
AIST  
AIHT  
47B Asynchronous Input Hold Time  
5,7  
ns  
ns  
48  
DSACKAsserted to BERR, HALT Asserted  
Data-Out Hold from CLKOUT High  
t
DABA  
DOCH  
53  
54  
55  
56  
t
0
0
0
ns  
CLKOUT High to Data-Out High Impedance  
R/W Asserted to Data Bus Impedance Change  
RESET Pulse Width (Reset Instruction)  
t
ns  
CHDH  
RADC  
HRPW  
t
80  
512  
590  
40  
512  
590  
25  
512  
590  
ns  
t
CLKOUT  
CLKOUT  
56A RESET Pulse Width (Input from External  
Device)  
t
RPWI  
57  
70  
71  
BERR Negated to HALT Negated (Rerun)  
t
0
0
60  
0
0
30  
0
0
20  
ns  
ns  
ns  
BNHN  
CLKOUT Low to Data Bus Driven (Show Cycle)  
t
t
SCLDD  
SCLDS  
Data Setup Time to CLKOUT Low (Show  
Cycle)  
30  
15  
10  
72  
80  
81  
82  
83  
84  
Data Hold from CLKOUT Low (Show Cycle)  
DSI Input Setup Time  
DSI Input Hold Time  
t
20  
30  
20  
30  
20  
10  
15  
10  
15  
10  
6
10  
6
ns  
ns  
ns  
ns  
ns  
ns  
SCLDH  
t
DSISU  
t
DSIH  
DSCLK Setup Time  
t
10  
6
DSCSU  
DSCLK Hold Time  
t
DSCH  
DSO Delay Time  
t
t
t
t
cyc  
+ 16  
cyc  
+ 50  
cyc  
+ 25  
DSOD  
MOTOROLA  
MC68340 USER’S MANUAL  
11-9  
For More Information On This Product,  
Go to: www.freescale.com  
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