Freescale Semiconductor, Inc.
10. For external clock w/PLL mode operation, the minimum CLKOUT pulse width is based on a 50% duty cycle.
11. For external clock mode, there is a 10–40 ns skew between the input clock signal and the output CLKOUT signal
from the MC68340. Clock skew is measured from the rising edges of the clock signals.
12. For external clock mode w/PLL, there is a 5 ns skew between the input clock signal and the output CLKOUT
signal from the MC68340. Clock skew is measured from the rising edges of the clock signals.
MOTOROLA
MC68340 USER’S MANUAL
11-7
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