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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
4.4 MC68340 INITIALIZATION SEQUENCE  
The following paragraphs discuss a suggested method for initializing the MC68340 after  
power-up.  
4.4.1 Startup  
RESET is asserted by the MC68340 during the time in which V  
is ramping up, the VCO  
CC  
is locking onto the frequency, and the MC68340 is going through the reset operation. After  
RESET is negated, four bus cycles are run, with global CS0 being asserted to fetch the  
32-bit supervisor stack pointer (SSP) and the 32-bit program counter (PC) from the boot  
ROM. Until programmed differently, CS0 is a global, 16-bit-wide, three-wait-state chip  
select. CS0 can be programmed to continue decode for a range of addresses after the  
V-bit is set, provided the desired address range is first loaded into the CS0 base address  
register. After the V-bit is set for CS0, global chip select can only be restarted with a  
system reset.  
After the SSP and the PC are fetched, the module base address register (MBAR) should  
be initialized, and the MBAR V-bit should be set (CPU space address $0003FF00) with  
the desired base address for the internal modules.  
4.4.2 SIM40 Module Configuration  
The order of the following SIM40 register initializations is not important; however, time can  
be saved by initializing the SYNCR first to quickly increase to the desired processor  
operating frequency. The module base address register must be initialized prior to any of  
following steps.  
Clock Synthesizer Control Register (SYNCR):  
• Set frequency control bits (W, X, Y) to specify frequency.  
• Select action taken during loss of crystal (RSTEN bit): activate a system reset or  
operate in limp mode.  
• Select system clock and CLKOUT during LPSTOP (STSIM and STEXT bits).  
Module Configuration Register (MCR)  
• If using the software watchdog, periodic interrupt timer, and/or the bus monitor, select  
action taken when FREEZE is asserted (FRZx bits).  
• Select port B configuration (FIRQ bit). Note that this bit is used in combination with  
the bits in the PPARB to program the function of the port B pins.  
• Select the access privilege for the supervisor/user registers (SUPV bit).  
• Select the interrupt arbitration level for the SIM40 (IARBx bits).  
Autovector Register (AVR)  
• Select the desired external interrupt levels for internal autovectoring.  
4- 36  
MC68340 USER’S MANUAL  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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