Freescale Semiconductor, Inc.
***************************************************************************
* Initialization code
***************************************************************************
* Start Chip Select Initialization:
INIT340
MOVE.W
#$2700,SR
Init SR - interrupts masked
***************************************************************************
* Set up default module base address value
MOVEQ.L #7,D0
MOVEC.L D0,DFC
MBAR is in CPU space
load DFC to indicate CPU space
Set address/valid bit
MOVE.L
MOVES.L
#MODBASE+1,D0
D0,MBAR
write to MBAR
***************************************************************************
* Set up system protection register:
* Software watchdog disabled, double bus fault monitor disabled, bus
* monitor BERR after 16 clocks.
MOVE.B
#6,SYPCR+MODBASE
***************************************************************************
* Clock synthesizer control register:
* Switch from 8.3 to 16.7 MHZ
MOVE.W
#$7F00,SYNCR+MODBASE
X-bit doubles the default speed
***************************************************************************
* Module configuration register:
* When FREEZE is asserted, software watchdog and periodic interrupt timer
* are disabled, bus monitor is enabled. Port B = 4 IRQs, 4 chip selects.
* Show Cycles enabled, external arbitration enabled. Supervisor/user
* SIM registers unrestricted, Interrupt Arbitration at priority $F
MOVE.W
#$420F,MCR+MODBASE
***************************************************************************
* Now, set up Address masks and base addresses for the chip selects:
LEA
MOVEQ
CSAM0+MODBASE,A0 Point to CS0 addr. mask location.
#7,D
Set up a loop counter.
LEA
CSAM0$,A1
(A1)+,(A0)+
D0,LOOP
Point to addr mask memory location.
Init. addr mask and base addr reg
LOOP MOVE.L
DBRA
MOTOROLA
MC68340 USER’S MANUAL
4- 39
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