Freescale Semiconductor, Inc.
Development Support
Background Debug Mode
BKGD pin during host-to-target transmissions to speed up rising edges.
Since the target does not drive the BKGD pin during this period, there is
no need to treat the line as an open-drain signal during host-to-target
transmissions.
B CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START
TARGET SENSES BIT
OF BIT TIME
EARLIEST
START OF
NEXT BIT
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
Figure 18-1. BDM Host to Target Serial Bit Timing
B CLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
HIGH-IMPEDANCE
TARGET MCU
SPEEDUP PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
PERCEIVED
START OF BIT
TIME
R-C RISE
BKGD PIN
10 CYCLES
10 CYCLES
EARLIEST
START OF
NEXT BIT
HOST SAMPLES
BKGD PIN
Figure 18-2. BDM Target to Host Serial Bit Timing (Logic 1)
MC68HC912DG128 — Rev 3.0
Technical Data
Development Support
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