Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
Section 18. Development Support
18.1 Contents
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
18.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .357
18.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
18.6 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
18.2 Introduction
Development support involves complex interactions between
MC68HC912DG128 resources and external development systems. The
following section concerns instruction queue and queue tracking signals,
background debug mode, and instruction tagging.
18.3 Instruction Queue
The CPU12 instruction queue provides at least three bytes of program
information to the CPU when instruction execution begins. The CPU12
always completely finishes executing an instruction before beginning to
execute the next instruction. Status signals IPIPE[1:0] provide
information about data movement in the queue and indicate when the
CPU begins to execute instructions. This makes it possible to monitor
CPU activity on a cycle-by-cycle basis for debugging. Information
available on the IPIPE[1:0] pins is time multiplexed. External circuitry
can latch data movement information on rising edges of the E-clock
signal; execution start information can be latched on falling edges. Table
18-1 shows the meaning of data on the pins.
MC68HC912DG128 — Rev 3.0
Technical Data
Development Support
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