Freescale Semiconductor, Inc.
MSCAN Controller
17.13.15 msCAN12 Port CAN Control Register (PCTLCAN)
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
PUPCAN
0
Bit 0
RDPCAN
0
PCTLCAN
$013D
R
W
RESET
0
0
0
0
0
0
The following bits control pins 7 through 2 of Port CAN when they are
implemented externally.
PUPCAN — Pull-Up Enable Port CAN
0 = Pull mode disabled for Port CAN.
1 = Pull mode enabled for Port CAN.
RDPCAN — Reduced Drive Port CAN
0 = Reduced drive disabled for Port CAN.
1 = Reduced drive enabled for Port CAN.
17.13.16 msCAN12 Port CAN Data Register (PORTCAN)
Bit 7
PCAN7
-
6
5
4
3
2
1
Bit 0
PORTCAN
$013E
R
TxCAN
RxCAN
PCAN6
PCAN5
-
PCAN4
PCAN3
-
PCAN2
W
RESET
-
-
Port bits 7 to 2 will read zero when configured as inputs because they
are not implemented externally.
When configured as output, port bits 7 to 2 will read the last value
written.
Reading bits 1 and 0 returns the value of the TxCan and RxCan pins,
respectively.
17.13.17 msCAN12 Port CAN Data Direction Register (DDRCAN)
Bit 7
DDCAN7
0
6
DDCAN6
0
5
DDCAN5
0
4
DDCAN4
0
3
DDCAN3
0
2
DDCAN2
0
1
0
Bit 0
0
DDRCAN
$013F
R
W
RESET
0
0
DDCAN7 – DDCAN2 — This bits served as memory locations since
there are no corresponding external port pins.
Technical Data
MC68HC912DG128 — Rev 3.0
MSCAN Controller
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