Freescale Semiconductor, Inc.
MSCAN Controller
17.13.11 msCAN12 Receive Error Counter (CRXERR)
Bit 7
6
5
4
3
2
1
Bit 0
CRXERR
$010E
R
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
W
RESET
0
0
0
0
0
0
0
0
This register reflects the status of the msCAN12 receive error counter.
The register is read only.
17.13.12 msCAN12 Transmit Error Counter (CTXERR)
Bit 7
6
5
4
3
2
1
Bit 0
CTXERR
$010F
R
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
W
RESET
0
0
0
0
0
0
0
0
This register reflects the status of the msCAN12 transmit error counter.
The register is read only.
NOTE: Both error counters must only be read when in SLEEP or SOFT_RESET
mode.
17.13.13 msCAN12 Identifier Acceptance Registers (CIDAR0–7)
On reception each message is written into the background receive
buffer. The CPU is only signalled to read the message however, if it
passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message is overwritten by the next
message (dropped).
The acceptance registers of the msCAN12 are applied on the IDR0 to
IDR3 registers of incoming messages in a bit by bit manner.
For extended identifiers all four acceptance and mask registers are
applied. For standard identifiers only the first two (CIDMR0/1 and
CIDAR0/1) are applied. In the latter case it is required to program the
three last bits (AM2 – AM0) in the mask register CIDMR1 to ‘don’t care’.
Technical Data
MC68HC912DG128 — Rev 3.0
MSCAN Controller
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