Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
17.13.10 msCAN12 Identifier Acceptance Control Register (CIDAC)
Bit 7
0
6
0
5
IDAM1
0
4
IDAM0
0
3
0
2
1
Bit 0
CIDAC
$0108
R
IDHIT2
IDHIT1
IDHIT0
W
RESET
0
0
0
0
0
0
IDAM1 – IDAM0 — Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organisation (see Identifier Acceptance Filter). Table 17-7
summarizes the different settings. In Filter Closed mode no
messages are accepted such that the foreground buffer is never
reloaded.
Table 17-8. Identifier Acceptance Mode Settings
IDAM1
IDAM0
Identifier Acceptance Mode
Two 32 bit Acceptance Filters
Four 16 bit Acceptance Filters
Eight 8 bit Acceptance Filters
Filter Closed
0
0
1
1
0
1
0
1
IDHIT2 – IDHIT0 — Identifier Acceptance Hit Indicator
The msCAN12 sets these flags to indicate an identifier acceptance hit
(see Identifier Acceptance Filter). Table 17-7 summarizes the
different settings.
Table 17-9. Identifier Acceptance Hit Indication
IDHIT2
IDHIT1
IDHIT0
Identifier Acceptance Hit
Filter 0 Hit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Filter 1 Hit
Filter 2 Hit
Filter 3 Hit
Filter 4 Hit
Filter 5 Hit
Filter 6 Hit
Filter 7 Hit
The IDHIT indicators are always related to the message in the
foreground buffer. When a message gets copied from the background to
the foreground buffer the indicators are updated as well.
NOTE: The CIDAC register can only be written if the SFTRES bit in CMCR0 is
set.
MC68HC912DG128 — Rev 3.0
Technical Data
MSCAN Controller
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