Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
OVRIF — Overrun Interrupt Flag
This flag is set when a data overrun condition occurs. If not masked,
an Error interrupt is pending while this flag is set.
0 = No data overrun has occurred.
1 = A data overrun has been detected.
RXF — Receive Buffer Full
The RXF flag is set by the msCAN12 when a new message is
available in the foreground receive buffer. This flag indicates whether
the buffer is loaded with a correctly received message. After the CPU
has read that message from the receive buffer the RXF flag must be
handshaken (cleared) in order to release the buffer. A set RXF flag
prohibits the exchange of the background receive buffer into the
foreground buffer. If not masked, a Receive interrupt is pending while
this flag is set.
0 = The receive buffer is released (not full).
1 = The receive buffer is full. A new message is available.
WARNING: To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
NOTE: The CRFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
17.13.7 msCAN12 Receiver Interrupt Enable Register (CRIER)
Bit 7
WUPIE
0
6
RWRNIE
0
5
TWRNIE
0
4
RERRIE
0
3
TERRIE
0
2
BOFFIE
0
1
OVRIE
0
Bit 0
RXFIE
0
CRIER
$0105
R
W
RESET
WUPIE — Wake-up Interrupt Enable
0 = No interruptis generated from this event.
1 = A wake-up event results in a wake-up interrupt.
RWRNIE — Receiver Warning Interrupt Enable
0 = No interruptis generated from this event.
1 = A receiver warning status event results in an error interrupt.
MC68HC912DG128 — Rev 3.0
Technical Data
MSCAN Controller
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