Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
Section 17. MSCAN Controller
17.1 Contents
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
17.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
17.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
17.5 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .318
17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
17.7 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .324
17.8 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
17.9 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
17.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
17.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .332
17.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .338
17.2 Introduction
The MC68HC912DG128 has two identical msCAN12 modules,
identified as CAN0 and CAN1. The information to follow describes one
fsCAN unless specifically noted and register locations specifically
relate to CAN0. CAN1 registers are located 512 bytes from CAN0.
The fsCAN12 is the specific implementation of the Freescale scalable
CAN (fsCAN) concept targeted for the Freescale M68HC12
microcontroller family.
MC68HC912DG128 — Rev 3.0
Technical Data
MSCAN Controller
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