Freescale Semiconductor, Inc.
Analog-to-Digital Converter
The channel from which this result was obtained is dependent on the
conversion mode selected. The registers are always read-only in normal
mode.
16.5 ATD Mode Operation
STOP — causes all clocks to halt (if the S bit in the CCR is zero). The
system is placed in a minimum-power standby mode. This aborts any
conversion sequence in progress.
WAIT — ATD conversion continues unless AWAI bit in ATDxCTL2
register is set.
BDM — Debug options available as set in register ATDxCTL3.
USER — ATD continues running unless ADPU is cleared.
ADPU — ATD operations are stopped if ADPU = 0, but registers are
accessible.
Technical Data
MC68HC912DG128 — Rev 3.0
Analog-to-Digital Converter
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