Freescale Semiconductor, Inc.
Inter-IC Bus
Clear
IBIF
Master
Mode
?
Y
N
Arbitration
Lost
?
Y
TX
RX
Tx/Rx
?
N
Last Byte
Clear IBAL
Transmitted
?
Y
N
N
Last
Byte To Be Read
?
N
Y
RXAK=0
?
IAAS=1
?
IAAS=1
?
Y
N
Y
Y
N
Data Transfer
Address Transfer
Y
End Of
Addr Cycle
(Master Rx)
?
2nd Last
Byte To Be Read
?
(Read)
Y
Y
SRW=1
?
RX
TX/RX
?
TX
(Write)
N
N
N
Y
ACK From
Receiver
?
Write Next
Byte To IBDR
Generate
Stop Signal
Set TX
Mode
Set TXAK =1
N
Read Data
From IBDR
And Store
Tx Next
Byte
Write Data
To IBDR
Switch To
Rx Mode
Set RX
Mode
Switch To
Rx Mode
Read Data
From IBDR
And Store
Dummy Read
From IBDR
Generate
Stop Signal
Dummy Read
From IBDR
Dummy Read
From IBDR
RTI
Figure 15-4. Flow-Chart of Typical IIC Interrupt Routine
Technical Data
MC68HC912DG128 — Rev 3.0
Inter-IC Bus
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