Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Registers
Bit 7
EDG7B
0
6
EDG7A
0
5
EDG6B
0
4
EDG6A
0
3
EDG5B
0
2
EDG5A
0
1
EDG4B
0
Bit 0
EDG4A
0
RESET:
TCTL3 — Timer Control Register 3
$008A
Bit 7
EDG3B
0
6
EDG3A
0
5
EDG2B
0
4
EDG2A
0
3
EDG1B
0
2
EDG1A
0
1
EDG0B
0
Bit 0
EDG0A
0
RESET:
TCTL4 — Timer Control Register 4
$008B
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge
detector circuits.
Table 13-2Edge Detector Circuit Configuration
EDGnB
EDGnA
Configuration
Capture disabled
0
0
1
1
0
1
0
1
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
Bit 7
C7I
0
6
C6I
0
5
4
3
C3I
0
2
C2I
0
1
C1I
0
Bit 0
C0I
0
C5I
C4I
RESET:
0
0
TMSK1 — Timer Interrupt Mask 1
$008C
Read or write anytime.
MC68HC912DG128 — Rev 3.0
Technical Data
Enhanced Capture Timer
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