Freescale Semiconductor, Inc.
Clock Functions
11.8 Clock Divider Chains
Figure 11-6, Figure 11-7, Figure 11-8, and Figure 11-9 summarize the
clock divider chains for the various peripherals on the
68HC(9)12DG128.
BCSP BCSS
1:x
TCLKs
T CLOCK
GENERATOR
SYSCLK
PHASE
LOCK
LOOP
PLLCLK
TO CPU
÷2
ECLK
PCLK
E AND P
CLOCK
GENERATOR
EXTALi
TO
BUSES,
SPI,
EXTAL
XTAL
BCSP BCSS
0:0
PWM,
ATD0, ATD1
REDUCED
CONSUMPTION
OSCILLATOR
EXTALi
CLKSRC = 1
CLKSRC = 0
BCSP BCSS
0:1
EXTALi
TO
MSCAN
MCS = 0
TO
SCI0, SCI1,
ECT
MCLK
MCS = 1
SLOW MODE
CLOCK
DIVIDER
SLWCLK
÷ 2
SYNC
XCLK
TO
RTI, COP
TO CAL
CLKSW = 0
CLKSW = 1
÷ 2
SYNC
BDMCLK
TO BDM
TO CLOCK
MONITOR
Figure 11-6. Clock Generation Chain
Technical Data
MC68HC912DG128 — Rev 3.0
Clock Functions
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