欢迎访问ic37.com |
会员登录 免费注册
发布采购

68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
 浏览型号68HC912DG128PV8的Datasheet PDF文件第175页浏览型号68HC912DG128PV8的Datasheet PDF文件第176页浏览型号68HC912DG128PV8的Datasheet PDF文件第177页浏览型号68HC912DG128PV8的Datasheet PDF文件第178页浏览型号68HC912DG128PV8的Datasheet PDF文件第180页浏览型号68HC912DG128PV8的Datasheet PDF文件第181页浏览型号68HC912DG128PV8的Datasheet PDF文件第182页浏览型号68HC912DG128PV8的Datasheet PDF文件第183页  
Freescale Semiconductor, Inc.  
Clock Functions  
System Clock Frequency formulas  
11.7 System Clock Frequency formulas  
See Figure 11-6:  
SLWCLK = EXTALi / ( 2 x SLOW )  
SLWCLK = EXTALi  
SLOW = 1,2,..63  
SLOW = 0  
PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)  
ECLK = SYSCLK / 2  
XCLK = SLWCLK / 2  
PCLK = SYSCLK / 2  
BCLK(1) = EXTALi / 2  
Boolean equations:  
SYSCLK = (BCSP & PLLCLK) | (BCSP & BCSS & EXTALi) | (BCSP &  
BCSS & SLWCLK)  
MCLK = (PCLK & MCS) | (XCLK & MCS)  
MSCAN system = (EXTALi & CLKSRC) | (SYSCLK & CLKSRC)  
BDM system = (BCLK & CLKSW) | (ECLK & CLKSW)  
NOTE: During limp-home mode PCLK, ECLK, BCLK, MCLK and XCLK are  
supplied by VCO (PLLCLK).  
1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.  
MC68HC912DG128 — Rev 3.0  
Technical Data  
Clock Functions  
For More Information On This Product,  
Go to: www.freescale.com  
 复制成功!