Freescale Semiconductor, Inc.
Clock Functions
Clock Divider Chains
PCLK
5-BIT MODULUS
COUNTER (PR0-PR4)
TO ATD0
and ATD1
÷ 2
÷ 2
REGISTER: SP0BR
BITS: SPR2, SPR1, SPR0
0:0:0
SPI
BIT RATE
÷ 2
÷ 2
÷ 2
0:0:1
0:1:0
MSCAN
CLOCK
EXTALi
CLKSRC
SYSCLK
ECLK
0:1:1
÷ 2
÷ 2
÷ 2
÷ 2
1:0:0
1:0:1
1:1:0
1:1:1
CLKSW
BDM BIT CLOCK:
BCLK
Receive: Detect falling edge,
count 12 ECLKs, Sample input
BKGD IN
SYNCHRONIZER
Transmit 1: Detect falling edge,
count 6 ECLKs while output is
high impedance, Drive out 1 E
cycle pulse high, high imped-
ance output again
BKGD DIRECTION
BKGD OUT
BKGD
PIN
LOGIC
Transmit 0: Detect falling edge,
Drive out low, count 9 ECLKs,
Drive out 1 E cycle pulse high,
high impedance output
Figure 11-9. Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM
MC68HC912DG128 — Rev 3.0
Technical Data
Clock Functions
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