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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Clock Functions  
Limp-Home and Fast STOP Recovery modes  
LOCK — Locked Phase Lock Loop Circuit  
Regardless of the bandwidth control mode (automatic or manual):  
0 = PLL VCO is not within the desired tolerance of the target  
frequency.  
1 = After the phase lock loop circuit is turned on, indicates the PLL  
VCO is within the desired tolerance of the target frequency.  
Write has no effect on LOCK bit. This bit is cleared in limp-home mode as  
the lock detector cannot operate without the reference frequency.  
LHIF — Limp-Home Interrupt Flag  
0 = No change in LHOME bit.  
1 = LHOME condition has changed, either entered or exited limp-  
home mode.  
To clear the flag, write one to this bit in PLLFLG.  
LHOME — Limp-Home Mode Status  
0 = MCU is operating normally, with EXTALi clock available for  
generating clocks or as PLL reference.  
1 = Loss of reference clock. CGM delivers PLL VCO limp-home  
frequency to the MCU.  
For Limp-Home mode, see Limp-Home and Fast STOP Recovery modes.  
Bit 7  
LOCKIE  
0
6
5
AUTO  
1
4
ACQ  
0
3
0
0
2
PSTP  
0
1
LHIE  
0
Bit 0  
PLLON  
NOLHM  
(1)  
(2)  
RESET:  
PLLCR — PLL Control Register  
1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.  
2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.  
$003C  
Read and write anytime. Exceptions are listed below for each bit.  
LOCKIE — PLL LOCK Interrupt Enable  
0 = PLL LOCK interrupt is disabled  
1 = PLL LOCK interrupt is enabled  
Forced to 0 when VDDPLL=0.  
MC68HC912DG128 — Rev 3.0  
Technical Data  
Clock Functions  
For More Information On This Product,  
Go to: www.freescale.com  
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