Freescale Semiconductor, Inc.
Clock Functions
Acquisition and Tracking Modes
11.5 Acquisition and Tracking Modes
The lock detector compares the frequencies of the VCO feedback clock,
DIVCLK, and the final reference clock, REFCLK. Therefore, the speed
of the lock detector is directly proportional to the final reference
frequency. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
The PLL filter is manually or automatically configurable into one of two
operating modes:
• Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL start-
up or when the PLL has suffered a severe noise hit and the VCO
frequency is far off the desired frequency. This mode can also be
desired in harsh environments when the leakage levels on the
filter pin (XFC) can overcome the tracking currents of the PLL
charge pump. When in acquisition mode, the ACQ bit in the PLL
control register is clear.
• Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. The PLL enters tracking
mode when the VCO frequency is nearly correct. The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically. With an identical filtering time constant, the
PLL bandwidth is larger in acquisition mode than in tracking by a ratio of
about 3.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, PLLCLK, is safe to use as the source for the base clock,
SYSCLK. If PLL LOCK interrupt requests are enabled, the software can
wait for an interrupt request and then check the LOCK bit. If CPU
interrupts are disabled, software can poll the LOCK bit continuously
(during PLL start-up, usually) or at periodic intervals. In either case,
when the LOCK bit is set, the PLLCLK clock is safe to use as the source
MC68HC912DG128 — Rev 3.0
Technical Data
Clock Functions
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