Freescale Semiconductor, Inc.
Clock Functions
Phase-Locked Loop (PLL)
T1CLK
T2CLK
T3CLK
T4CLK
INT ECLK
PCLK
XCLK
CANCLK
Figure 11-1. Internal Clock Relationships
11.4 Phase-Locked Loop (PLL)
The phase-locked loop (PLL) of the 68HC(9)12DG128 is designed for
robust operation in an Automotive environment. The allowed PLL crystal
or ceramic resonator reference of 0.5 to 8MHz is selected for the wide
availability of components with good stability over the automotive
temperature range. Please refer to Figure 11-6 in section Clock Divider
Chains for an overview of system clocks.
NOTE: When selecting a crystal, it is recommended to use one with the lowest
possible frequency in order to minimise EMC emissions.
An oscillator design with reduced power consumption allows for slow
wait operation with a typical power supply current less than a milli-
ampere. The PLL circuitry can be bypassed when the VDDPLL supply is
at VSS level. In this case, the PLL module is powered down and the
oscillator output transistor has a stronger transconductance for improved
drive of higher frequency resonators (as the crystal frequency needs to
be twice the maximum bus frequency). Refer to Figure 3-3 in Pinout and
Signal Descriptions.
MC68HC912DG128 — Rev 3.0
Technical Data
Clock Functions
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