Freescale Semiconductor, Inc.
Clock Functions
for the base clock. See Clock Divider Chains. If the VCO is selected as
the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate
action, depending on the application.
The following conditions apply when the PLL is in automatic bandwidth
control mode:
• The ACQ bit is a read-only indicator of the mode of the filter.
• The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆trk, and is cleared when the VCO frequency is out of a
certain tolerance, ∆unt. See 19 Electrical Characteristics.
•
The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆Lock, and is cleared when the VCO frequency is out of
a certain tolerance, ∆unl. See 19 Electrical Characteristics.
• CPU interrupts can occur if enabled (LOCKIE = 1) when the lock
condition changes, toggling the LOCK bit.
The PLL also can operate in manual mode (AUTO = 0). All LOCK
features described above are active in this mode, only the bandwidth
control is disabled. Manual mode is used mainly for systems operating
under harsh conditions (e.g.uncoated PCBs in automotive
environments). When this is the case, the PLL is likely to remain in
acquisition mode. The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• In case tracking is desired (ACQ = 1), the software must wait a
given time, tacq, after turning on the PLL by setting PLLON in the
PLL control register. This is to avoid switching to tracking mode
too early while the XFC voltage level is still too far away from its
quiescent value corresponding to the target frequency. This
operation would be very detrimental to the stabilization time.
Technical Data
MC68HC912DG128 — Rev 3.0
Clock Functions
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