Freescale Semiconductor, Inc.
Clock Functions
VCO clock at its minimum frequency, f VCOMIN, is provided as the system
clock, allowing the MCU to continue operating.
The MCU is said to be operating in “limp-home” mode with the forced
VCO clock as the system clock. PLLON and BCSP (‘bus clock select
PLL’) signals are forced high and the MCS (‘module clock select’) signal
is forced low. The LHOME flag in the PLLFLG register is set to indicate
that the MCU is running in limp-home mode. A change of this flag sets
the limp-home interrupt flag, LHIF, and if enabled by the LHIE bit, the
limp-home mode interrupt is requested. The Clock Monitor is enabled
irrespective of CME and FCME bit settings. Module clocks to the RTI &
COP (XCLK), BDM (BCLK) and ECT & SCI (MCLK) are forced to be
PCLK (at f VCOMIN) and ECLK is also equal to f VCOMIN. MSCAN clock
select is unaffected.
EXTALi
A
B
Clock Monitor Fail
0 --> 4096
0 --> 4096
13-stage counter
(Clocked by XCLK)
Limp-Home
BCSP
Restore BCSP
PLLCLK (Limp-Home)
SYSCLK
Restore PLLCLK or EXTALi
Figure 11-3. Clock Loss during Normal Operation
The clock monitor is polled each time the 13-stage free running counter
reaches a count of 4096 XCLK cycles i.e. mid-count, hence the clock
status gets checked once every 8192 XCLK cycles. When the presence
of an external clock is detected, the MCU exits limp-home mode,
clearing the LHOME flag and setting the limp-home interrupt flag. Upon
leaving limp-home mode, BCSP and MCS signals are restored to their
Technical Data
MC68HC912DG128 — Rev 3.0
Clock Functions
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