Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
Usage Notes
The equations for t , t , and t are dependent on the actual initial and
15
5
tot
final clock periods t and t , not the nominal. This means the variability
1
2
in the ICLK frequency due to process, temperature, and voltage must be
considered. Additionally, other process factors and noise can affect the
actual tolerances of the points at which the filter changes modes. This
means a worst case adjustment of up to 35 percent (ICLK clock period
tolerance plus 10 percent) must be added. This adjustment can be
reduced with trimming. Table 8-4 shows some typical values for settling
time.
Table 8-4. Typical Settling Time Examples
t
t
t
t
t
tot
N
84
21
1
1
2
15
5
1/ (6.45 MHz)
1/ (25.8 MHz)
1/ (25.8 MHz)
1/ (307.2 kHz)
1/ (25.8 MHz)
1/ (6.45 MHz)
1/ (307.2 kHz)
1/ (25.8 MHz)
430 µs
107 µs
141 µs
11.9 ms
535 µs
212 µs
246 µs
12.0 ms
850 µs
525 µs
560 µs
12.3 ms
84
8.5.7 Improving Settling Time
The settling time of the internal clock generator can be vastly improved
if an external clock source can be used during the settling time. When
the internal clock generator is disabled (ICGON is low), the DDIV[3:0]
and DSTG[7:0] bits can be written. Then, when the internal clock
generator is re-enabled, the clock period will automatically start at the
point written in the DDIV and DSTG bits.
Since a change in the DDIV and DSTG bits only cause a change in the
clock period relative to the starting point, the starting point must first be
captured. The initial clock period can be expressed as in the next
example, where t is a process, temperature, and voltage dependent
X
constant and DDIV1 and DSTG1 are the values of DDIV and DSTG
when operating at t .
1
DDIV1
t1 = tX
2
DSTG1
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
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Internal Clock Generator Module (ICG)
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