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68HC908RFRK2 参数 Datasheet PDF下载

68HC908RFRK2图片预览
型号: 68HC908RFRK2
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 [Advance Information]
分类和应用:
文件页数/大小: 250 页 / 2075 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Internal Clock Generator Module (ICG)  
Usage Notes  
8.5.6 Nominal Frequency Settling Time  
Because the clock period of the internal clock (ICLK) is dependent on the  
digital loop filter outputs (DDIV and DSTG) which cannot change  
instantaneously, ICLK will temporarily operate at an incorrect clock  
period when any of the operating condition changes. This happens  
whenever the part is reset, the ICG multiply factor (N) is changed, the  
ICG trim factor (TRIM) is changed, or the internal clock is enabled after  
inactivity (STOP or disabled operation). The time that the ICLK takes to  
adjust to the correct period is known as the settling time.  
Settling time depends primarily on how many corrections it takes to  
change the clock period, and the period of each correction. Since the  
corrections require four periods of the low-frequency base clock  
(4*t  
), and since ICLK is N (the ICG multiply factor for the desired  
IBASE  
frequency) times faster than IBASE, each correction takes 4*N*t  
The period of ICLK, however, will vary as the corrections occur.  
.
ICLK  
8.5.6.1 Settling to Within 15 Percent  
When the error is greater than 15 percent, the filter takes eight  
corrections to double or halve the clock period. Due to how the DCO  
increases or decreases the clock period, the total period of these eight  
corrections is approximately 11 times the period of the fastest correction.  
(If the corrections were perfectly linear, the total period would be 11.5  
times the minimum period; however, the ring must be slightly non-linear.)  
Therefore, the total time it takes to double or halve the clock period is  
44*N*t  
.
ICLKFAST  
If the clock period needs more than doubled or halved, the same  
relationship applies, only for each time the clock period needs doubled,  
the total number of cycles doubles.  
That is, when transitioning from fast to slow:  
Going from the initial speed to half speed takes 44*N*t  
ICLKFAST  
From half speed to quarter speed takes 88*N*t  
ICLKFAST  
Going from quarter speed to eighth speed takes 176*N*t  
and so on.  
,
ICLKFAST  
MC68HC908RFRK2  
MOTOROLA  
AdvanceInformation  
129  
Internal Clock Generator Module (ICG)  
For More Information On This Product,  
Go to: www.freescale.com  
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