Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
x
This series can be expressed as (2 –1)*44*N*t
, where x is the
ICLKFAST
x
number of times the speed needs doubled or halved. Since 2 happens
to be equal to t
/t
, the equation reduces to
ICLKSLOW ICLKFAST
44*N*(t
-t
). Note that increasing speed takes much
ICLKSLOW ICLKFAST
longer than decreasing speed since N is higher. This can be expressed
in terms of the initial clock period (t ) minus the final clock period (t ) as
1
2
such:
t15 = abs[44N(t1 – t2)]
8.5.6.2 Settling to Within 5 Percent
Once the clock period is within 15 percent of the desired clock period,
the filter starts making smaller adjustments. When between 15 percent
and 5 percent error, each correction will adjust the clock period between
1.61 percent and 2.94 percent. In this mode, a maximum of eight
corrections will be required to get to less than 5 percent error. Since the
clock period is relatively close to desired, each correction takes
approximately the same period of time, or 4*t
. At this point, the
IBASE
internal clock stable bit (ICGS) will be set and the clock frequency is
usable, although the error will be as high as 5 percent. The total time to
this point is:
t5 = abs[44N(t1 – t2)] + 32tIBASE
8.5.6.3 Total Settling Time
Once the clock period is within 5 percent of the desired clock period, the
filter starts making minimum adjustments. In this mode, each correction
will adjust the frequency between 0.202 percent and 0.368 percent. A
maximum of 24 corrections will be required to get to the minimum error.
Each correction takes approximately the same period of time or 4*t
.
IBASE
Added to the corrections for 15 percent to 5 percent, this makes 32
corrections (128*t ) to get from 15 percent to the minimum error.
IBASE
The total time to the minimum error is:
t
= abs[44N(t1 – t2)] + 128tIBASE
tot
Advance Information
130
MC68HC908RFRK2
MOTOROLA
Internal Clock Generator Module (ICG)
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