Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
DDIV and DSTG, the output of the DCO can change only in quantized
steps as the DLF increments or decrements its output. The following
sections describe how each block will affect the output frequency.
8.5.4.1 Digitally Controlled Oscillator
The digitally controlled oscillator (DCO) is an inaccurate oscillator which
generates the internal clock (ICLK), whose clock period is dependent on
the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]). Because of the
digital nature of the DCO, the clock period of ICLK will change in
quantized steps. This will create a clock period difference or quantization
error (Q-ERR) from one cycle to the next. Over several cycles or for
longer periods, this error is divided out until it reaches a minimum error
of 0.202 percent to 0.368 percent. The dependence of this error on the
DDIV[3:0] value and the number of cycles the error is measured over is
shown in Table 8-3.
Table 8-3. Quantization Error in ICLK
t
Q-ERR
DDIV[3:0]
%0000 (min)
%0000 (min)
%0001
ICLK Cycles
Bus Cycles
ICLK
4
≥ 32
4
1
1.61%–2.94%
0.202%–0.368%
0.806%–1.47%
0.202%–0.368%
0.403%–0.735%
0.202%–0.368%
0.202%–0.368%
0.202%–0.368%
0.202%–0.368%
≥ 8
1
%0001
≥ 16
4
≥ 4
1
%0010
%0010
≥ 8
≥ 4
≥ 2
≥ 1
≥ 2
≥ 1
≥ 1
≥ 1
%0011
%0100
%0101–%1001 (max)
8.5.4.2 Binary Weighted Divider
The binary weighted divider divides the output of the ring oscillator by a
power of 2, specified by the DCO divider control bits (DDIV[3:0]). DDIV
maximizes at %1001 (values of %1010 through %1111 are interpreted
as %1001), which corresponds to a divide by 512. When DDIV is %0000,
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MC68HC908RFRK2
Internal Clock Generator Module (ICG)
MOTOROLA
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