Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
9.5 A/D Conversion Data Register (ADC)
8
2
This register contains the output of the A/D converter. See Figure 9-1.
Bit 7
AD7
6
5
4
3
2
1
Bit 0
AD0
3
Read:
Write:
Reset:
AD6
AD5
AD4
AD3
AD2
AD1
ADC
$001D
4
X
X
X
X
X
X
X
X
= Unimplemented
5
Figure 9-2. A/D Conversion Data Register
6
9.6 A/D Subsystem During Wait/Halt Modes
7
The A/D subsystem continues normal operation during wait and halt modes. To
decrease power consumption during wait or halt, the ADON bit in the ADSC
register and the EERC bit in the EEPROG register should be cleared if the A/D
subsystem is not being used.
8
9
9.7 A/D Subsystem Operation During Stop Mode
10
11
12
13
14
A
When the stop mode is enabled, execution of the STOP instruction will terminate
all A/D subsystem functions. Any pending conversion is aborted. When the
oscillator resumes operation upon leaving the stop mode, a finite amount of time
passes before the A/D subsystem stabilizes sufficiently to provide conversions at
its rated accuracy. The delays built into the MC68HC805P18 when coming out of
stop mode are sufficient for this purpose. No explicit delays need to be added to
the application software.
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
MC68HC805P18
9-6
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