Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
If the ADON bit is set and an input from channels 0 through 4 is selected, the
corresponding port C pin’s DDR bit will be cleared (making that port C pin an input).
If the port C data register is read while the A/D is on and one of the shared input
channels is selected using bit CH0 through CH2, the corresponding port C pin will
read as a logic zero. The remaining port C pins will read normally. To digitally read
a port C pin, the A/D subsystem must be disabled (ADON = 0) or input channel 5
through 7 must be selected.
8
2
3
4
Table 9-1. A/D Multiplexer Input
Channel Assignments
5
Channel
Signal
AD0 — Port C, Bit 6
AD1 — Port C, Bit 5
AD2 — Port C, Bit 4
AD3 — Port C, Bit 3
0
1
2
3
4
5
6
7
6
7
8
V
— Port C, Bit 7
REFH
(V
+ V )/2
9
REFH
SS
V
SS
10
11
12
13
14
A
Reserved
16
17
18
19
20
ANALOG-TO-DIGITAL CONVERTER
Rev. 1.0
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