Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
NOTE
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2
Execution of the STOP instruction without conversion to halt (via
MOR1) will cause the oscillator to stop, and therefore disable the
COP watchdog timer. If the COP watchdog timer is to be used, the
stop mode should be changed to the halt mode by programming the
appropriate option in MOR1.
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4
6.4.2 Halt Mode
5
Execution of the STOP instruction with the conversion to halt places the MCU in
this low-power mode. Halt mode consumes the same amount of power as wait
mode (both halt and wait modes consume more power than stop mode).
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7
In halt mode the PH2 clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be generated
from the 16-bit timer or a reset to be generated from the COP watchdog timer.
Execution of the STOP instruction automatically clears the I bit in the condition
code register enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
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A
If the 16-bit timer interrupt is enabled, it will cause the processor to exit the halt
mode and resume normal operation. The halt mode also can be exited when an
IRQ external interrupt (or port A, if selected as an option in the MOR2) or external
RESET occurs. When exiting the halt mode, the PH2 clock will resume after a
delay of one to 4064 PH2 clock cycles. This varied delay time is the result of the
halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of
the stop mode), which has been free-running (a feature of the wait mode).
NOTE
The halt mode is not intended for normal use. This feature is provided
to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently.
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OPERATING MODES
Rev. 1.0
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