Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8
2
SECTION 3
CENTRAL PROCESSING UNIT
3
4
3.1 Introduction
This section describes the CPU registers.
5
6
3.2 CPU Registers
The five CPU registers are shown in Figure 3-1 and the interrupt stacking order are
shown in Figure 3-2.
7
8
7
7
0
0
0
0
A
X
ACCUMULATOR
INDEX REGISTER
9
10
11
12
13
14
A
12
PC
1
PROGRAM COUNTER
STACK POINTER
12
0
7
1
0
0
0
0
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
16
17
18
19
20
CENTRAL PROCESSING UNIT
Rev. 1.0
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
