Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
READ
WRITE
REGISTER
UNIMPLEMENTED
RESERVED
ADDR
7
6
5
4
3
2
1
0
8
2
R
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
W
R
3
W
R
0
0
0
0
0
0
TIMER CONTROL REGISTER
TCR
ICIE
ICF
OCIE
OCF
TOIE
TOF
IEDG
0
OLVL
0
W
R
4
TIMER STATUS REGISTER
TSR
W
R
5
ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0
INPUT CAPTURE MSB
ICRH
W
R
6
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
INPUT CAPTURE LSB
ICRL
W
R
7
OUTPUT COMPARE MSB
OCRH
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
W
R
8
OUTPUT COMPARE LSB
OCRL
OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
W
R
TIMER MSB
TMRH
9
W
R
TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0
ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0
TIMER LSB
TMRL
10
11
12
13
14
A
W
R
ALTERNATE COUNTER MSB
ACRH
W
R
ALTERNATE COUNTER LSB
ACRL
W
R
0
0
EEPROM Programming
Register
CPEN
AD6
ER1
AD4
ER0
AD3
LATCH EERC EEPGM
W
R
AD7
CC
AD5
AD2
AD1
AD0
A/D CONVERSION DATA
ADC
W
R
0
0
A/D STATUS AND CONTROL
ADSC
ADON
CH2
CH1
CH0
W
R
RESERVED
W
16
17
18
19
20
UNIMPLEMENTED
RESERVED
Figure 2-4. MC68HC805P18 I/O and Control Registers $0010-$001F
MEMORY
MC68HC805P18
2-6
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