Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
READ
WRITE
REGISTER
ADDR
7
6
5
4
3
2
1
0
8
2
R
PORT A DATA
PORTA
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PA7
PB7
PA6
PB6
PA5
PB5
PC5
PD5
PA4
0
PA3
0
PA2
0
PA1
0
PA0
0
W
R
PORT B DATA
PORTB
W
R
3
PORT C DATA
PORTC
PC7
PD7
PC6
0
PC4
1
PC3
0
PC2
0
PC1
0
PC0
0
W
R
4
PORT D DATA
PORTD
W
R
5
PORT A DATA DIRECTION
DDRA
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
W
R
6
1
1
1
1
1
PORT B DATA DIRECTION
DDRB
DDRB7 DDRB6 DDRB5
W
R
7
PORT C DATA DIRECTION
DDRC
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
W
R
0
0
0
0
0
0
0
PORT D DATA DIRECTION
DDRD
8
DDRD5
W
R
UNIMPLEMENTED
9
W
R
UNIMPLEMENTED
10
11
12
13
14
A
W
R
0
0
0
0
0
0
0
0
0
0
0
SIOP CONTROL REGISTER
SCR
SPE
MSTR
0
W
R
SPIF
DCOL
SIOP STATUS REGISTER
SSR
W
R
SIOP DATA REGISTER
SDR
SDR7
SDR6
SDR5
SDR4
SDR3
SDR2
SDR1
SDR0
W
R
UNIMPLEMENTED
UNIMPLEMENTED
UNIMPLEMENTED
W
R
W
R
W
16
17
18
19
20
UNIMPLEMENTED
RESERVED
Figure 2-3. MC68HC805P18 I/O and Control Registers $0000–$000F
MEMORY
Rev. 1.0
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