August 27, 1998
GENERAL RELEASE SPECIFICATION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC3
$002B
R
W
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
reset:
Figure 11-8. D/A Data Register 3 (DAC3) (MSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC3
R
$002C
W
D1
0
D0
0
reset:
0
0
0
0
0
0
Figure 11-9. D/A Data Register 3 (DAC3) (LSB)
A value of $0000 loaded into these registers results in a continuously low output
on the corresponding PWM output pin. A value of $0200 results in a 50% duty
cycle output, and so on. The maximum value, $03FF corresponds to an output
which is at “1” for 1023/1024 of the cycle.
1024T
$000
1023T
$001
512T
512T
$200
$3FF
1023T
T = 2 x t
CYC
Figure 11-10. PWM Output Waveform Examples
A new value written to the a D/A register pair will not be effective until the end of
the current PWM period. This provides a monotonic change of the DC component
of the output without overshoots or vicious starts (a vicious start is an output
which gives totally erroneous PWM during the initial period following an update of
the PWM registers). This feature is achieved by double buffering of the PWM D/A
registers.
11.2 MUX CHANNEL ENABLE REGISTER (MCER)
Since the PWM output pins PWM0-PWM3 are multiplexed with the standard I/O
port pins PA0-PA3 respectively, the MCER is provided to switch between the PWM
and standard I/O function for each pin.
MC68HC05SB7
REV 2.1
PULSE WIDTH MODULATOR
MOTOROLA
11-3
FREESCALE [ Freescale ]
