GENERAL RELEASE SPECIFICATION
August 27, 1998
11.1 D/A DATA REGISTERS (DAC0-DAC3)
Each PWM channel is programmed with a 10-bit data, in two 8-bit registers.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC0
$0025
R
W
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
reset:
Figure 11-2. D/A Data Register 0 (DAC0) (MSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC0
$0026
R
W
D1
0
D0
0
reset:
0
0
0
0
0
0
Figure 11-3. D/A Data Register 0 (DAC0) (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC1
$0027
R
W
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
reset:
Figure 11-4. D/A Data Register 1 (DAC1) (MSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC1
$0028
R
W
D1
0
D0
0
reset:
0
0
0
0
0
0
Figure 11-5. D/A Data Register 1 (DAC1) (LSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC2
$0029
R
W
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
reset:
Figure 11-6. D/A Data Register 2 (DAC2) (MSB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DAC2
$002A
R
W
D1
0
D0
0
reset:
0
0
0
0
0
0
Figure 11-7. D/A Data Register 2 (DAC2) (LSB)
MOTOROLA
11-2
PULSE WIDTH MODULATOR
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
