August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 11
PULSE WIDTH MODULATOR
The PWM subsystem contains four 10-bit PWM channels, which can be used as
independent D/A converters. Figure 11-1 shows the block diagram for the Pulse
Width Modulator, with channel 0 in details.
Internal Bus
Channel 0
10-bit Counter
f
÷ 2
OP
10-bit D/A 0
Data Register
10-bit D/A 0
Data Register
Buffer
D/A 0 Multiplexer
To
Channel 1
To
Channel 2
To
Channel 3
Zero
Detector
Comparator
S
PWM0
pin
Latch
R
Figure 11-1. PWM Block Diagram
The PWM cycle time is 2048 times the MCU internal processor clock (f or f
).
BUS
OP
Duty cycle of the PWM outputs can be programmed by the corresponding D/A
Data Registers (DAC0-DAC3).
MC68HC05SB7
REV 2.1
PULSE WIDTH MODULATOR
MOTOROLA
11-1
FREESCALE [ Freescale ]
