August 27, 1998
GENERAL RELEASE SPECIFICATION
COPON — COP ON
COPON is a write-once bit.
1 = Enables COP watchdog system.
0 = No effect on system.
NOTE
If the voltage on the IRQ/V pin exceeds 2 × V , the COP watchdog is disabled,
PP
DD
and remains disabled until the IRQ/V voltage falls below 2 × V .
PP
DD
9.4
9.5
CORE TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the timer remains active. If the
interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT
mode.
CORE TIMER DURING STOP MODE
The Core Timer is cleared when going into STOP mode. When STOP is exited by
an external interrupt or an external RESET, the internal oscillator will resume, fol-
lowed by 4064 cycles internal processor stabilization delay. The timer is then
cleared and operation resumes.
MC68HC05SB7
REV 2.1
CORE TIMER
MOTOROLA
9-5
FREESCALE [ Freescale ]
