GENERAL RELEASE SPECIFICATION
August 27, 1998
Power on clears the entire counter chain and begins clocking the counter. After
the startup delay (16 or 4064 internal clock cycles) the power on reset circuit is
released, clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or four cycles
of the internal clock. A timer overflow function at the eighth counter stage allows a
timer interrupt every 1024 internal clock cycles.
9.3
COP WATCHDOG
Four counter stages at the end of the Core Timer make up the computer operating
properly (COP) watchdog.The COP watchdog timeout period is shown in Table 9-
1.
A timeout of the COP watchdog generates a COP reset. The COP watchdog is
part of a software error detection system and must be cleared periodically to start
a new timeout period. To clear the COP watchdog and prevent a COP reset, write
a logic “0” to the COPC bit of the COP register at location $1FF0.
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
COPR
$1FF0
R
0
COPC
0
W
reset:
U
U
U
U
U
U
U
U = UNAFFECTED BY RESET
Figure 9-4. COP Watchdog Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 = No effect on system.
0 = Reset COP watchdog timer.
The COP Watchdog reset will assert the pulldown device to pull the RESET pin
low for three to four clock cycles of the internal bus clock.
After a POR or reset, the COP watchdog is disabled. It is enabled b writing a logic
“1” to the COPON bit in the Miscellaneous Control Register (see Figure 9-5).
Once enabled, the COP watchdog can only be disabled by a POR or reset.
BIT 7
TSEN
0
BIT 6
LVRON
1
BIT 5
BIT 4
SCLK
0
BIT 3
CSSEL
0
BIT 2
TCSEL
0
BIT 1
BIT 0
MCR
R
0
COPON
0
ESVEN SMINLEV
$000B
W
reset:
0
0
U = UNAFFECTED BY RESET
Figure 9-5. Miscellaneous Control Register (MCR)
MOTOROLA
9-4
CORE TIMER
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
