August 27, 1998
GENERAL RELEASE SPECIFICATION
RTIFR — Real-Time Interrupt Flag Reset
Writing a logic one to this write only bit clears the RTIF bit. RTIFR always reads
as a logic zero. Reset does not affect RTIFR.
1 = Clear RTIF flag bit.
0 = No effect on RTIF flag bit.
RT1, RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real time interrupt rates, as shown in
Table 9-1. Because the selected RTI output drives the COP watchdog, chang-
ing the real time interrupt rate also changes the counting rate of the COP
watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout period
and real-time interrupt period.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may cause
a real time interrupt request to be missed or an additional real time interrupt
request to be generated. Therefore, the COP timer should be cleared (by writing a
just before changing RT1 and RT0.
Table 9-1. Core Timer Interrupt Rates and COP Timeout Selection
Minimum COP
Timeout Period
(7 or 8 RTI Periods)
Timer Overflow Interrupt
Real-Time Interrupt
(RTI) Period
10
(TOF) Period (f ÷ 2 )
OP
RT1 RT0
RTI Rate
f
=
f
=
f
=
f
=
f
=
f
=
OP
OP
OP
OP
OP
OP
2.1 MHz
1.0 MHz
2.1 MHz
7.81 ms
15.6 ms
31.3 ms
62.5 ms
1.0 MHz
16.4 ms
32.8 ms
65.5 ms
131 ms
2.1 MHz
54.7 ms
109 ms
219 ms
438 ms
1.0 MHz
114 ms
229 ms
458 ms
916 ms
14
0
0
1
1
0
1
0
1
f
f
f
f
÷ 2
÷ 2
÷ 2
÷ 2
OP
OP
OP
OP
15
16
17
488 µs
1024 µs
9.2
CORE TIMER COUNTER REGISTER (CTCR)
A 15-stage ripple counter is the basis of the Core Timer.The value of the first eight
stages is readable at any time from the read only timer counter register as shown
in Figure 9-2.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CTCR
$0009
R
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
W
reset:
0
0
0
0
0
0
0
0
Figure 9-3. Core Timer Counter Register (CTCR)
MC68HC05SB7
REV 2.1
CORE TIMER
MOTOROLA
9-3
FREESCALE [ Freescale ]
