GENERAL RELEASE SPECIFICATION
August 27, 1998
9.1
CORE TIMER STATUS AND CONTROL REGISTER
The read/write Core Timer status and control register contains the interrupt flag
bits, interrupt enable bits, interrupt flag bit resets, and the rate selects for the real
time interrupt as shown in Figure 9-2.
BIT 7
BIT 6
RTIF
BIT 5
CTOFE
0
BIT 4
RTIE
0
BIT 3
BIT 2
BIT 1
RT1
1
BIT 0
RT0
1
CTSCR
$0008
R
CTOF
0
CTOFR
0
0
RTIFR
0
W
reset:
0
0
Figure 9-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Flag
This read only flag becomes set when the first eight stages of the Core Timer
counter roll over from $FF to $00. The CTOF flag bit generates a timer overflow
interrupt request if CTOFE is also set. The CTOF flag bit is cleared by writing a
logic one to the CTOFR bit. Writing to CTOF has no effect. Reset clears CTOF.
1 = Overflow in Core Timer has occurred.
0 = No overflow of Core Timer since CTOF last cleared.
RTIF — Real Time Interrupt Flag
This read only flag becomes set when the selected RTI output becomes active.
RTIF generates a real time interrupt request if RTIE is also set. The RTIF
enable bit is cleared by writing a logic one to the RTIFR bit. Writing to RTIF has
no effect. Reset clears RTIF.
1 = Overflow in real time counter has occurred.
0 = No overflow of real time counter since RTIF last cleared.
CTOFE — Core Timer Overflow Interrupt Enable
This read/write bit enables Core Timer overflow interrupts. Reset clears
CTOFE.
1 = Core Timer overflow interrupts enabled.
0 = Core Timer overflow interrupts disabled.
RTIE — Real-Time Interrupt Enable
This read/write bit enables real time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled.
0 = Real-time interrupts disabled.
CTOFR — Core Timer Overflow Flag Reset
Writing a logic one to this write only bit clears the CTOF bit. CTOFR always
reads as a logic zero. Reset does not affect CTOFR.
1 = Clear CTOF flag bit.
0 = No effect on CTOF flag bit.
MOTOROLA
9-2
CORE TIMER
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
