August 27, 1998
GENERAL RELEASE SPECIFICATION
SECTION 9
CORE TIMER
This section describes the operation of the Core Timer and the Computer
Operating Properly (COP) watchdog timer. Figure 9-1 shows a block diagram of
the Core Timer.
RESET
INTERNAL
CLOCK (f
)
OP
$0009
OVERFLOW
CORE TIMER COUNTER REGISTER
÷ 4
÷ 2
OSC1 (f
)
OSC
BITS 0–7 OF 15-STAGE
RIPPLE (COUNT-UP) COUNTER
f
÷1024
OP
CORE TIMER
INTERRUPT
REQUEST
$0008
CORE TIMER STATUS/CONTROL REGISTER
RESET
RTI RATE SELECT
$1FF0
COP REGISTER
17
16
15
14
f
÷2
f
÷2
f
÷2
f ÷2
OP
OP
OP
OP
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
POWER-ON
RESET
COP
WATCHDOG
RESET
S
R
Q
÷ 2
÷ 2
÷ 2
÷ 2
RESET
Figure 9-1. Core Timer Block Diagram
MC68HC05SB7
REV 2.1
CORE TIMER
MOTOROLA
9-1
FREESCALE [ Freescale ]
