GENERAL RELEASE SPECIFICATION
August 27, 1998
5.3.3 Low Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage on
the V pin falls below the LVR trip voltage. The LVR will assert the pulldown
DD
device to pull the RESET pin low for three to four clock cycles of the internal bus
clock. The Low Voltage Reset circuit is enabled/disabled by the LVRON bit in the
Miscellaneous Control Register (see Figure 5-2).
LVRON — LVR ON
This is a read/write bit to disable/enable the LVR circuit.
0 = Low Voltage Reset circuit disabled.
1 = Low Voltage Reset circuit enabled. This is the default setting at POR
or reset.
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the EPROM (locations $0600 –
$1DFF and $1FF0 - $1FFF) or the RAM (locations $0030 – $010F) generates an
illegal address reset. The illegal address reset will assert the pulldown device to
pull the RESET pin low for 3 - 4 cycles of the internal bus clock.
5.4
RESET STATES
The following paragraphs describe how the various resets initialize the MCU.
5.4.1 CPU
A reset has the following effects on the CPU:
•
•
•
Loads the stack pointer with $FF.
Sets the I bit in the condition code register, inhibiting interrupts.
Loads the program counter with the user defined reset vector from
locations $1FFE and $1FFF.
•
•
Clears the stop latch, enabling the CPU clock.
Clears the wait latch, bringing the CPU out of the wait mode.
5.4.2 I/O Registers
A reset has the following effects on I/O registers:
•
Clears bits in data direction registers configuring pins as inputs:
– DDRA7 – DDRA0 in DDRA for port A.
– DDRB7 – DDRB1 in DDRA for port B.
– DDRC3–DDRC0 in DDRA for port C.
•
•
Has no effect on port A, B or C data registers.
Sets the IRQE bit in the interrupt status and control register.
MOTOROLA
5-4
RESETS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
